1. Field of the Invention
The present invention is related generally to local power supplies for integrated circuits with a high clock frequency, and in particular to circuits for use in limiting inductance-induced ripple voltage in integrated circuits with high dynamic power consumption.
2. Description of Related Art
Over the past few years clock speeds of central processing units (CPUs) have increased from a few MHz to 500 MHz or more. This increase in clock speed requires that components within the CPU, i.e., the CPU core, as well as components that communicate with the CPU operate at ever increasing clock speeds.
The increase in CPU clock speeds has been accompanied by an increase in the number of transistors on the CPU die, i.e. in the integration on the chip. The greater integration results in a larger die size, which in turn means that some circuits on the die are separated by greater distances, and in addition, more pins are required to take information to and from the die. Both of these effects complicate electromagnetic interference (EMI) shielding at the higher clock speeds.
FIG. 1 is a first order lumped model of a typical CPU configuration as seen by the power supply pins. A first inductor 145 represents the inductance of the board plane and via layer, and is connected to power supply line 110. Connected in series with inductor 145 is a second inductor 140 that represents the inductance of the socket and packaging of the CPU. Connected in series with inductors 140 and 145 is a series combination of a third inductor 137 and a resistor 135. The series combination of third inductor 137 and resistor 135 represents the inductance and resistance, respectively of either a ball grid array, or a lead frame with bond wires, and the power grid of CPU 100. The CPU die has an intrinsic RC characteristic that is represented by a series combination of resistor 151 and capacitor 152 connected to resistor 135 by local power supply line 110A and to ground line 111 by local power supply line 111A.
Typically, at the start of each clock cycle, many elements in CPU 100 change state, which in turn causes a momentary increase in current draw, i.e. the current draw changes as a function of time. The voltage generated by inductors 145, 140 and 137 is directly proportional to the changes in current with respect to time. Specifically, as the time derivative of the current increases, inductors 145, 140, 137 create a positive voltage drop which in turn reduces the voltage across local power supply lines 110A and 111A. Consequently, sufficient power cannot be provided instantaneously to the elements in the CPU core changing state, and so the voltage difference between local power supply lines 110A and 111A decreases, i.e., collapses.
However, once the various elements have switched state, the change in current draw with respect to time diminishes and the voltage difference recovers. In addition, inductors 145, 140, and 137 supplement the voltage across local power supply lines 110A and 111A because the time derivative of the current is negative.
These swings in voltages caused by the inherent inductances, including parasitic inductances, in response to changes in the current draw over time, are called inductance-induced ripple voltages or sometimes simply bounce. The inductance-induced ripple voltages have many undesirable features. For example, if the voltage collapse is too great, operation of CPU 100 can become unreliable. Also, the inductance-induced ripple voltages radiate from at least the pins of the circuit, and can radiate from power supply lines in CPU 100, that function as antennas. This requires additional shielding or other design changes to assure that CPU 100 complies with all relevant EMI standards. Additionally, if the frequency of the inductance-induced ripple voltage approaches the resonance frequency of the package, the voltage collapse and EMI noise is effectively amplified which in turn further exacerbates the problems associated with the parasitic inductances.
Various techniques have been used to minimize the effects of the inductance-induced ripple voltages in attempting to provide a stable power supply voltage across a CPU core. Specifically, power supply decoupling was normally achieved by placing banks of capacitors on the die between the local power supply lines carrying power supply and ground potentials so as to minimize the effects of parasitic inductances and resistances. However, each bank of capacitors has a limited band in the frequency spectrum where the bank is effective in smoothing out the inductance-induced ripple voltage, and has a limited capacity to decouple.
Moreover, as both the power consumption and the clocking speeds increased, the switching current at local power nodes within the integrated circuit required a relatively large capacitance to offset the power losses associated with the parasitic board and package inductances near the resonance frequency of the package. This, in turn, meant that a larger of number of high frequency capacitors were required.
However, as the high frequency circuits become more highly integrated, the real estate on the die available for capacitors diminished as the requirement for the number of capacitors increased due to the increased power consumption. This limitation forced consideration of alternative physical and manufacturing configurations to provide the required amount of passive capacitance.
A first approach was to connect passive capacitance 160 on the board between the CPU socket power supply connectors and ground, i.e. between the connection of inductors 145 and 140 and ground as illustrated in FIG. 2A. It should be understood that passive capacitance 160 includes parasitic inductance and resistance that are connected in series with passive capacitance 160. However, this approach was not completely successful because this configuration did not effectively offset the effects of inductors 140 and 137.
Consequently, some manufacturers use discrete capacitors that are placed on top or below the package. In this configuration, passive capacitance 165 is connected between inductors 140 and 137 and ground as illustrated in FIG. 2B. While this configuration is better than the configuration of FIG. 2A, passive capacitance 165 does not directly affect the voltage across local power supply lines 110A and 111A.
Hence, other manufacturers include a separate chip of low inductance capacitors in the package containing the high frequency die and attempt to connect capacitance 170 on the separate chip between local power supply line 110A and 111A as shown in FIG. 2C.
While the current manufacturing techniques and physical configurations may be adequate for current microprocessor clock speeds and power consumption, as the power consumption and clock speeds continue to increase other solutions will be required. Unfortunately, the next generation of high-speed circuits will draw even more power, because typically the power consumption is proportional to the clock speed. With the higher power consumption and the fast clock speeds, the changes in the time derivative of the current will be more extreme which in turn indicates problems associated with inductance-induced ripple voltages will be further exacerbated.
The solution to power supply inductance-induced ripple voltages appears to be limited to the use of passive capacitors. Other techniques for offsetting the effects of parasitic inductance and resistance are not of use considering the feature sizes of the next generation of integrated circuits. Consequently, the dynamic power consumption of future generations of circuits may be limited by the inability to effectively offset the effects of parasitic inductances and resistances on power supply voltages.